1. Field of the Invention
The present invention relates generally to data transmission technology and, more specifically, the present invention relates to the sensing of differential signals.
2. Background Information
Differential data communications signals rarely have 50% duty cycles. Therefore, their frequency spectrum generally includes a DC component. If differential data communications signal duty cycle varies continuously, as is usually the case, then the DC component also varies. If such a signal is sent through a medium, which blocks the DC component, an undesirable phenomenon known as baseline wander occurs. If baseline wander is not cancelled out or compensated for, the phenomenon can cause increased bit-error rate (BER), which results in a serious degradation in performance.
FIG. 1A illustrates a typical data communication medium 101 through which a DC signal component cannot pass. This medium includes a transmitter, modeled as a voltage source 103, a source impedance, modeled as source resistors 105 and 107 having a resistance of R.sub.S /2, a cable 109, an isolation transformer 111, and the receiver, modeled as load resistor R.sub.L 113. FIG. 1B illustrates the simplified equivalent circuit of the medium 151. The inductor L 153, which models the transformer inductance, shorts out any DC component and only allows AC components to pass through to R.sub.L 155. As a result, no DC signal component from the transmitter, which includes voltage source 157 and source resistors 159 and 161, can pass through medium 151.
FIG. 2 illustrates baseline wander for the case of a differential signal, i.e., a signal not referenced to ground, that is transmitted through the circuits 101 and 151 of FIGS. 1A and 1B, respectively. As shown in FIG. 2, the baseline 205 of the input signal IN 201 is constant at 0 volts. In contrast, the baseline 205 of the output signal OUT 203 decreases asymptotically from 0 volts to a negative value.
In general, the baseline asymptote of a differential signal having a constant duty cycle D is given by Equation 1 below. ##EQU1## V.sub.BASE is the baseline voltage and V.sub.P-P is the peak-to-peak differential amplitude of the signal.
In the example in FIG. 2, D equals 0.75. Thus, the baseline asymptote equals -V.sub.P-P /4 in accordance with Equation 1 above. It is noted, however, that the duty cycle generally varies continuously so that the baseline 205 varies or wanders continuously.
A device that receives a differential signal such as OUT 203 converts the differential signal to a logic signal for subsequent processing using a comparator whose threshold is set midway between the two levels of the received signal. With the threshold set in this fashion, the receiver noise margin is maximized. If the baseline wanders, however, then the difference between the peak voltage of the received signal and the comparator threshold is no longer constant, but, rather, also varies along with the baseline. As the peak voltage varies, the comparator switches at different times with respect to the locations of transitions in the received signal. This introduces jitter that reduces timing margins in the clock and data recovery circuit that follows the comparator. The reduction in timing margin causes an increase in the bit-error rate.